A variety of memory applications, such as SRAM, DRAM, thin capacitively coupled thyristor applications and others, include a read-or-write bank having a set of memory cells for read-or-write data access. In a minimally prescribed amount of time (hereinafter a “bank cycle”), data is read from or written to a subset of those cells (hereinafter a “word”). The read-or-write access rate of such a memory is the frequency at which read or write operations may be performed, and is comparable to the inverse of the bank cycle time, with the bank cycle time increasing as the capacity of the bank increases.
An array of read-or-write banks can be combined in a read-or-write memory to attain a large memory capacity while keeping the bank cycle time of the memory to a minimum. In such a memory, a “memory cycle” is the time in which a word can be read from or written to the read-or-write memory via access to an appropriate read-or-write bank. Thus, the memory cycle time of the memory is typically comparable to or greater than the bank cycle time. The read-or-write access rate of such a memory array is the frequency at which read or write operations can be performed, and is comparable to the inverse of the memory cycle time.
Read-modify-write data access is another type of data access that is desirable in a variety of memory applications. In such applications, one or more words of data are read from memory, modified and written back into the memory. For brevity, further discussion is limited to single words with the understanding that this following discussion of example embodiments can be extended to multiple words of data.
In some instances, read-or-write memory has been utilized to support read-modify-write operations. For example, one memory cycle can be used to read a word that is subsequently modified over a period of zero or more memory cycles. The word is then written back to the memory in another memory cycle. The modification of the data does not actually use the memory: therefore, other memory accesses may be interleaved during the period of time during which the data is being modified. Thus, this read-or-write memory has a read-modify-write access using two memory operations, with two corresponding memory cycles, from the read-or-write memory. Therefore, the read-modify-write access rate of the memory (e.g., the frequency with which read-modify-write operations may be performed) has been one half the read-or-write access rate.